A non-volatile memory device may be able to electrically erase and store data, and may be able to store data even when power is not supplied. Because of this ability, applications of non-volatile memory may be important in various fields. The non-volatile memory device may be divided into a NAND-type non-volatile memory device and a NOR-type non-volatile memory device. The NAND-type non-volatile memory device may be used for storing data. The NOR-type non-volatile memory device may be used for booting up various systems.
In a NOR-type non-volatile memory device, a plurality of memory cells, which may constitute a single transistor, may be connected to one bit line in parallel. One memory cell transistor may be connected between a drain connected to a bit line and a source region connected to a common source line. In the NOR-type non-volatile memory device, a current of a memory cell may be high, the memory cell may operate at high speed, and a contact of the bit line and the common source line may occupy a large area. Accordingly, it may be difficult for a NOR-type non-volatile memory device to be highly integrated.
In the NOR type non-volatile memory device, the memory cells may be connected to the bit line in parallel. Accordingly, if the threshold voltage of the memory cell transistor is lower than a voltage (commonly 0V) applied to the word line of a non-selected memory cell, current may flow between a source and a drain regardless of whether a selected memory cell is turned on or off. In this instance, all memory cells may be read to be turned on. To solve such a problem, a non-volatile memory device referred to as a split-gate type may be used.
A non-volatile memory device may be divided into a flash memory device, which may have a laminated gate of a FLOTOX structure, and a SONOS device, which may have a structure similar to that of a MOS transistor and may include a multi-layer gate insulating layer. The gate insulating layer of the SONOS device may be a multi-layer charge storage insulating layer and may have a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer may be sequentially laminated (oxide-nitride-oxide (ONO) layer). Since charges may be stored in a deep level trap that a nitride layer has, the SONOS device may have a higher reliability than the flash memory device. Moreover, SONOS devices may be capable of performing writing and erasing operations at a low voltage.
FIGS. 1A to 1C illustrate an example method of manufacturing a related art split gate-type non-volatile memory device.
Referring to FIG. 1A, a device isolation layer (not shown) may be formed in the direction of a bit line in parallel on semiconductor substrate 50, and may limit active region 51. Multi-layer charge storage layer 54, first conductive layer 56, and capping layers 58 and 60 may be formed to be parallel to a word line with a prescribed width on semiconductor substrate 50. In embodiments, the ONO layer may be used as the charge storage layer. In embodiments, capping layers may be formed by laminating silicon oxide layer 58, which may function as a buffer, and silicon nitride layer 60 used as a hard mask. Then, to form first conductive layer 56, to cure damaged sidewalls, an oxide process may be performed on the sidewalls of first conductive layer 56 to form sidewall insulating layers 62.
The multi-layer charge storage layer exposed on active region 51 may be removed, excluding portions of multi-layer charge storage layer 54 under first conductive layer 56. Gate insulating layer 64 may be formed on the exposed active region of the substrate.
Referring to FIG. 1B, second conductive layer 66 may be formed on gate insulating layer 64 and first conductive layer 56 (including silicon oxide layer 58 and silicon nitride layer 60). Photoresist pattern 68, which may have opening 67, may be formed on second conductive layer 66. Photoresist pattern 68 may be formed so that opening 67 may limit tops of first conductive layer 56 and active region 51. Part of second conductive layer 66 may be exposed by opening 67.
Referring to FIG. 1C, second conductive layer 66 may be etched using photoresist pattern 68 as an etching mask and the various layers (capping layers 58, 60, first conductive layer 56, and ONO layer 54) under second conductive layer 66 may be simultaneously etched. Therefore, a pair of split gates, including ONO layer 54, first conductive layer patterns 56a, capping layer patterns 58a and 60a, and second conductive layer patterns 66a, may be formed in active region 51 of the substrate. The split gates may extend from a top of capping layer pattern 60a to gate insulating layer 64, covering sidewalls of first conductive layer patterns 56a (including sidewall insulating layers 62), and may be formed in active region 51 of the substrate. The pair of split gates may constitute the word line and may be perpendicular to the bit line.
In the related art method, first conductive layer 56 and second conductive layer 66 may be formed, and may be etched in a single etching process. However, when the various layers are laminated, a step difference between the objects may be very high. Hence, it may be necessary to use etching equipment having high etching rate. A top of second conductive layer 66, which may be the uppermost layer, may therefore be damaged. That is, if photoresist 68 formed on second conductive layer 66 is not thick enough, photoresist 68 may be substantially or completely consumed during the etching process. A top of second conductive layer 66 may therefore be revealed. Hence, second conductive layer 66 may not be able to withstand the high etching rate, and may be damaged. FIG. 2 illustrates the potential damage to tops of conductive layer patterns 66a in the region A.